Low cost, high speed parallel FIR digital filters for Software Radio on FPGAs

This paper discusses full-parallel FIR filters for FPGAs using their application in Digital Down-Converters (DDCs) for Software Radio receivers as a background. A commercially available 4-channel, 40MHz DDC architecture implemented on a Xilinx Virtex-II FPGA is described as a basis and a 2-channel, 80MHz DDC system to be implemented on the same device is proposed. Various full-parallel filter structures are discussed and compared, leading to the transpose form FIR with multiplier graph/block being selected. This technique is described in detail along with example systems generated by the RSG HDL filter generation software and associated schematic viewer. Two implementations of the required low-pass decimation filters are generated and compared using RSG and the Xilinx Distributed Arithmetic core. The proposed 2-channel, 80MHz DDC is bit-true modelled in SystemView by Elanix, implemented in VHDL and verified via simulation. The proposed DDC using RSG filters is found to require less FPGA resource the original 4-channel, 40MHz DDC and the proposed DDC using Xilinx filters.