A memory-efficient parameterisable FPGA implementation of the cdma2000 Turbo codec

Originally used in deep space telemetry Turbo codes can now be found in standards for 3G mobile and digital television. This paper describes a highly parameterisable codec design, based around the cdma2000 codec. The codec can be optimally configured for different memory and latency requirements. This is achieved by selecting different parameters depending on the requirements of the user. The Turbo codec was tested using the Nallatech Bit Error Rate Test (BERT) FPGA based hardware emulation system. The results obtained in these tests show how the codec performs when parameters such as the component decoder implementation are altered. Conventional tests such as increasing the number of decoder iterations were also performed. Results obtained are compared to others already published for the cdma2000 Turbo code standard.