A Flexible, Event-Driven Digital Filter With Frequency Response Independent of Input Sample Rate

This paper presents a clockless digital filter able to process inputs of different rates and formats, synchronous or asynchronous, with no adjustment needed to handle each input type. The filter is designed using a mix of asynchronous and real-time digital hardware, and for this reason relies on neither a clock nor the input data rate for setting its frequency response. The modular architecture of the filter, including delay segments with separated data and timing paths and a pipelined multi-way adder, allows easy extensions for different data widths. The filter was used as part of an ADC/DSP/DAC system which maintains its frequency response intact for varying sample rates without requiring any internal change. This property is not possible for any synchronous DSP system. The 16-tap, 8-bit FIR filter, integrated in a 130 nm CMOS process, includes on-chip automatic delay tuning, and for certain inputs, has signal-to-error ratio which exceeds that of clocked systems.