A high performance SIMD processor for binary image processing

Author

Legat, Jean-Didier ; De Muelenaere, Pierre

Author_Institution

Image Recognition Integrated Syst. SA, Louvain-la-Neuve, Belgium

fYear

1990

fDate

13-16 May 1990

Abstract

A high-performance single-instruction, multiple-data (SIMD) processor based on a full-custom VLSI chip has been designed for binary image processing applications. This dedicated IC has been fabricated in a 3-μm NMOS technology and contains 48000 transistors. The architecture of the processor is described, and the chip description, which includes an original organization for both the data path and image memories, is highlighted. The processor is fully operational. It is used in applications like filtering, skeletonization, feature extraction, document processing, and optical character recognition

Keywords

MOS integrated circuits; VLSI; computerised picture processing; multiprocessing systems; parallel processing; 3 micron; NMOS technology; SIMD processor; architecture; binary image processing; data path; document processing; feature extraction; filtering; full-custom VLSI chip; image memories; optical character recognition; organization; single instruction multiple data processor; skeletonization; Arithmetic; Circuits; Computer architecture; Image processing; Image recognition; MOS devices; Parallel processing; Programmable logic arrays; Programmable logic devices; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124761

Filename

124761