Title :
An efficient representation for formal synthesis
Author :
Blumenrohr, Christian ; Eisenbiegler, Dirk
Author_Institution :
Inst. for Circuit Design & Fault Tolerance, Karlsruhe Univ., Germany
Abstract :
In the last years, performing synthesis by logical refinement has become an interesting alternative towards postsynthesis verification. The paper presents a case study about the complexity of formal synthesis programs within a given calculus. For a simple synthesis step, it discusses how one can efficiently implement circuit transformations with respect to the complexity of the logical transformations of the underlying calculus
Keywords :
circuit CAD; computational complexity; formal verification; high level synthesis; program verification; case study; circuit transformations; formal synthesis programs; logical refinement; logical transformations; postsynthesis verification; underlying calculus; Calculus; Circuit faults; Circuit synthesis; Computer bugs; Costs; Fault tolerance; Hardware; High level synthesis; Safety; Space exploration;
Conference_Titel :
System Synthesis, 1997. Proceedings., Tenth International Symposium on
Conference_Location :
Antwerp
Print_ISBN :
0-8186-7949-2
DOI :
10.1109/ISSS.1997.621670
