Title :
An efficient model for DSP code generation: performance, code size, estimated energy
Author :
Gebotys, Catherine H.
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Abstract :
The paper presents a model for simultaneous instruction selection, compaction, and register allocation. An arc mapping model, along with logical propositions is used to create an optimization model. Code is generated in fast cpu times and is optimized for minimum code size, maximum performance or estimated energy dissipation. Code generated for realistic DSP applications provides performance and code size improvements from 1.09 up to 2.18 times for the TMS320C2x processor compared to previous research and a commercial compiler. In all examples, up to 106 instructions are generated in under one cpu minute. This research is important for industry since DSP code can be efficiently generated with constraints on code size, performance and energy dissipation
Keywords :
optimising compilers; signal processing; software performance evaluation; software tools; DSP code generation performance; TMS320C2x processor; arc mapping model; code size; code size improvements; commercial compiler; efficient model; estimated energy; estimated energy dissipation; fast cpu times; logical propositions; maximum performance; minimum code size; optimization model; realistic DSP applications; register allocation; simultaneous instruction selection; Compaction; Computer industry; Costs; Digital signal processing; Digital signal processing chips; Energy dissipation; Read only memory; Registers; Throughput; Timing;
Conference_Titel :
System Synthesis, 1997. Proceedings., Tenth International Symposium on
Conference_Location :
Antwerp
Print_ISBN :
0-8186-7949-2
DOI :
10.1109/ISSS.1997.621674
