A real-time multi-kernel picture convolver

The model used for architectural optimization is discussed. It is then shown that the optimal architecture for 2-D convolution uses a 1-D convolution combinatorial operator to reduce the 2-D problem to a classical 1-D systolic array. Furthermore, for a given technology and chip area, if one tries to apply the proposed cost function to this architecture, it is possible to predict a practical bound for the kernel size of convolutions that can be implemented on one chip. Details are given of a 5×10 real-time convolver chip that exhibits several new features, including a multi-kernel mode