Title :
Memory system reliability improvement through associative cache redundancy
Author :
Lucente, M. ; Harris, C. ; Muir, R.
Author_Institution :
Mitre Corp., Bedford, MA, USA
Abstract :
A redundancy memory architecture that increases system memory reliability without incurring the memory access speed degradation or size impact that result from using error-correction coding or paper-swapping techniques have been developed. The architecture uses a small associative cache memory to provide redundant memory locations. Logic is provided to perform memory system testing and remapping of fault memory locations. A VLSI circuit has been developed that incorporates the features of the architecture as a proof-of-concept demonstration. This device has been designated the memory reliability enhancement peripheral (MREP)
Keywords :
VLSI; buffer storage; circuit reliability; content-addressable storage; fault tolerant computing; integrated memory circuits; memory architecture; redundancy; VLSI circuit; associative cache redundancy; fault memory locations; redundancy memory architecture; reliability improvement; remapping; testing; Cache memory; Circuit faults; Degradation; Logic devices; Logic testing; Memory architecture; Performance evaluation; Redundancy; Reliability; System testing;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124781
