Title :
A 32 Kbs on-chip memory with high port-multiplicity (5 reads and 2 writes) for effective implementation of shared memory systems
Author :
Tsang, Tony ; Li, Ching ; Kalluri, Madhusudan
Author_Institution :
InventraTM, Mentor Graphics Corp., Beaverton, OR, USA
Abstract :
In this paper, we discuss the design of a multi-port SRAM which is an essential component in a shared memory system. Proposed is an area efficient memory cell structure which is better in cell stability and more immune to cross-talk noise. Some special circuit techniques are employed in order to accommodate the high capacity (32 Kbs) and the high number of ports (5R and 2W) required by the application. The 7-port memory is implemented in a 0.25 μm CMOS technology. Analyses prove that 200 MHz high speed operation, low peak power and complex read-write access functionality are achieved. The authors also show that such a design can be easily extended and adapted to other shared memory systems
Keywords :
CMOS memory circuits; SRAM chips; cellular arrays; integrated circuit noise; shared memory systems; 0.25 micron; 200 MHz; 32 Kbit; CMOS technology; area efficient memory cell structure; capacity; cell stability; circuit techniques; cross-talk noise; multi-port SRAM; on-chip memory; peak power; port-multiplicity; read-write access functionality; shared memory systems; Buffer storage; Circuit testing; Graphics; Pins; Production systems; Read-write memory; Registers; Stability; System testing; Timing;
Conference_Titel :
VLSI '98. System Level Design. Proceedings. IEEE Computer Society Workshop on
Conference_Location :
Orlando, FL
Print_ISBN :
0-8186-8448-8
DOI :
10.1109/IWV.1998.667139
