A 6-ns 256-kbit BiCMOS TTL SRAM

Author

Akioka, Takashi ; Hiraishi, Atsushi ; Yamauchi, Tatsumi ; Yokoyama, Yuji ; Takahashi, Shigeru ; Iwamura, Masahiro ; Kobayashi, Yutaka ; Ide, Akira ; Gotou, Nobuyuki ; Onozawa, Kazunori ; Uchida, Hideaki

Author_Institution

Hitachi Ltd., Ibaraki, Japan

fYear

1990

fDate

13-16 May 1990

Abstract

A 6-ns 64K×4-b BiCMOS, transistor-transistor logic (TTL)-I/O SRAM has been developed. Fast access time is due to the combination of innovative circuits and a double-metal, double-polysilicon 0.8-μm Hi-BiCMOS process technology. The novel circuits include a reduced-stage BiCMOS decoder and a current-sense-type address transition detection circuit. The chip size is 4.25 mm×10 mm. Simulated internal delay time components of a critical path of the decoder are shown. Address access time is 6 ns at T_a=25°C, V_CC=5 V with a 30 pF load connected to the common I/O node

Keywords

BIMOS integrated circuits; SRAM chips; transistor-transistor logic; 0.8 micron; 256 kbit; 6 ns; BiCMOS TTL SRAM; Hi-BiCMOS process technology; access time; address transition detection circuit; current-sense-type; double-metal; double-polysilicon; reduced-stage BiCMOS decoder; static RAM, memory IC; transistor-transistor logic; BiCMOS integrated circuits; Capacitance; Cities and towns; Decoding; Delay effects; Driver circuits; Laboratories; Pulse amplifiers; Pulse circuits; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124787

Filename

124787