A high performance system-on-chip architecture for digital wideband radar receiver

A system-on-chip (SoC) architecture employed in the digital receiver for monopulse tracking radar applications applying linear frequency modulation (LFM) signals is proposed. The signal processing flow will then be decomposed into several time-division stages, and the corresponding system function will be achieved with software or hardware implementation way respectively. Thereafter, an optimized SoC architecture for digital receiver is illustrated, and the prototype structure in field programmable gate array (FPGA) is designed so that all the processing modules can be integrated in single FPGA chip. Finally, the experimental results prove the validity and engineering applicability of the proposed architecture.