Title :
Yet another multiplier architecture
Author :
Stearns, Chip ; Ang, Peng
Author_Institution :
LSI Logic Corp., Menlo Park, CA, USA
Abstract :
The VLSI multiplier architecture discussed makes advances over previous architectures in terms of layout density and flexibility in making speed/size tradeoffs. This multiplier design and a ripple adder were used in LSI Logic´s L64814 floating point processor for use in Sun Microsystem´s SPARC system architecture. The novel architectural design yielded a 56-by-56, 30 ns, nonpipelined, 4100 transistor/mm2, semi-custom, multiplier-accumulator. However, the architectural concept is general and flexible enough to accommodate any size multiplier and allow tradeoffs between a given multiplier´s area and speed
Keywords :
VLSI; digital arithmetic; integrated logic circuits; multiplying circuits; 30 ns; L64814 floating point processor; SPARC system architecture; VLSI; layout density; multiplier architecture; semicustom multiplier-accumulator; Application specific integrated circuits; Arithmetic; Encoding; Large scale integration; Logic; Pipeline processing; Propagation delay; Silicon; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124790
