Yet another multiplier architecture

The VLSI multiplier architecture discussed makes advances over previous architectures in terms of layout density and flexibility in making speed/size tradeoffs. This multiplier design and a ripple adder were used in LSI Logic´s L64814 floating point processor for use in Sun Microsystem´s SPARC system architecture. The novel architectural design yielded a 56-by-56, 30 ns, nonpipelined, 4100 transistor/mm², semi-custom, multiplier-accumulator. However, the architectural concept is general and flexible enough to accommodate any size multiplier and allow tradeoffs between a given multiplier´s area and speed