DocumentCode
2322153
Title
A Parallel Processing Hardware Architecture for Elliptic Curve Cryptosystems
Author
Sakiyama, Kazuo ; De Mulder, Elke ; Preneel, Bart ; Verbauwhede, Ingrid
Author_Institution
Katholieke Univ. Leuven
Volume
3
fYear
2006
fDate
14-19 May 2006
Abstract
We propose a parallel processing crypto-processor for elliptic curve cryptography (ECC) to speed up EC point multiplication. The processor consists of a controller that dynamically checks instruction-level parallelism (ILP) and multiple sets of modular arithmetic logic units accelerating modular operations. A case study of HW design with the proposed architecture shows that EC point multiplication over GF(p) and GF(2m) can be improved by a factor of 1.6 compared to the case of using single processing element
Keywords
Galois fields; cryptography; digital arithmetic; instruction sets; logic devices; parallel architectures; elliptic curve cryptosystems; instruction-level parallelism; modular arithmetic logic units; parallel processing hardware architecture; Acceleration; Arithmetic; Elliptic curve cryptography; Embedded system; Energy consumption; Hardware; Logic design; Parallel processing; Public key cryptography; Technological innovation;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech and Signal Processing, 2006. ICASSP 2006 Proceedings. 2006 IEEE International Conference on
Conference_Location
Toulouse
ISSN
1520-6149
Print_ISBN
1-4244-0469-X
Type
conf
DOI
10.1109/ICASSP.2006.1660801
Filename
1660801
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