Area-Efficient NEDA Architecture for The 1-D DCT/IDCT

Author

Chidanandan, Archana ; Bayoumi, Magdy

Author_Institution

Comput. Sci. & Software Eng., Rose-Hulman Inst. of Technol., Terre Haute, IN

Volume

3

fYear

2006

fDate

14-19 May 2006

Abstract

A new distributed arithmetic has been applied to the 1-D DCT to produce a low power, high throughput architecture. In this paper, we apply NEDA to the even-odd decomposition matrices of the 8times8 forward and inverse DCT. We show that, with the proposed approach, the number of adders required for the adder array for the forward DCT and the inverse DCT is fewer than required if NEDA is applied directly to the 8times8 DCT and IDCT matrices. This reduction results in power savings, without decreasing the throughput. Also, for the inverse DCT, the number of adder stages is reduced, resulting in faster decoding

Keywords

adders; decoding; discrete cosine transforms; distributed arithmetic; matrix algebra; 1D DCT-IDCT; adder array; area-efficient NEDA architecture; decoding; distributed arithmetic; even-odd decomposition matrices; forward DCT; inverse DCT; Arithmetic; Computer architecture; Computer science; Decoding; Discrete cosine transforms; Matrix decomposition; Power engineering computing; Read only memory; Software engineering; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech and Signal Processing, 2006. ICASSP 2006 Proceedings. 2006 IEEE International Conference on

Conference_Location

Toulouse

ISSN

1520-6149

Print_ISBN

1-4244-0469-X

Type

conf

DOI

10.1109/ICASSP.2006.1660811

Filename

1660811