A pseudo 2D analysis of the velocity saturation region for flash cell modeling

Author

Ragad, H. ; Bouchakour, R. ; Lalande, F. ; Portal, J.M. ; Mirabel, J.M.

Author_Institution

Departement Microelectronique et Telecommun., L2MP Polytech, Marseille, France

fYear

2004

fDate

15-17 Nov. 2004

Firstpage

92

Lastpage

99

Abstract

A pseudo-2D analysis of the velocity saturation region (VSR) integrated in an analytical drift-diffusion surface-potential-based model is proposed. This approach allows the determination of the spatial repartition along the saturated channel of the surface potential and the electrical field for the modeling of the channel hot electron injection (CHEI). This MOS model is the core of a flash model, allowing the DC and transient simulations of a flash memory. This pseudo-2D analysis is successfully validated on a reference TMOS in 0.35μm CMOS technology. Its application to flash memory is validated on a 0.18 μm flash devices by comparing measurement and simulation of transient threshold voltage.

Keywords

circuit analysis computing; flash memories; hot carriers; integrated circuit modelling; surface potential; 0.18 micron; 0.35 micron; CMOS technology; DC simulations; MOS model; channel hot electron injection; drift-diffusion surface-potential-based model; electrical field; flash cell modeling; flash model; pseudo 2D analysis; saturated channel; spatial repartition; surface potential; transient simulations; velocity saturation region; Analytical models; CMOS technology; Channel hot electron injection; Electric potential; Flash memory; Gaussian channels; Gaussian processes; Nonvolatile memory; Semiconductor device modeling; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Non-Volatile Memory Technology Symposium, 2004

Print_ISBN

0-7803-8726-0

Type

conf

DOI

10.1109/NVMT.2004.1380813

Filename

1380813