Title :
3.5 K gate 32-bit ALU using GaAs HFET technology
Author :
Leung, W. ; Teng, K. ; Faris, A. ; Hu, A. ; Ackner, L. ; Isbara, M. ; Reid, C. ; Poon, T.
Author_Institution :
AT&T Bell Lab., Allentown, PA, USA
Abstract :
A GaAs 32-b ALU circuit is described. The best performance is 100 ps delay per gate at 2 V power supply and 25°C ambient. The average power dissipation is about 0.8 mW per gate. Best wafer yield of 14% was observed. This indicate that high-speed circuits with 3.5 K gate complexity can be implemented in the present SARGIC HFET technology in a pilot line environment. The ALU chip has input data register and output data register which can be clocked by independent signals. The propagation delay through a critical path between the registers is measured by moving the output clock edge towards the input clock edge until the chip fails
Keywords :
III-V semiconductors; VLSI; digital arithmetic; field effect integrated circuits; gallium arsenide; integrated logic circuits; 0.8 mW; 100 ps; 2 V; ALU chip; GaAs; HFET technology; SARGIC; SFFL; high-speed circuits; propagation delay; source follower FET logic; Circuits; Clocks; Gallium arsenide; HEMTs; MODFETs; Power dissipation; Power supplies; Propagation delay; Registers; Semiconductor device measurement;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124792
