3.5 K gate 32-bit ALU using GaAs HFET technology

A GaAs 32-b ALU circuit is described. The best performance is 100 ps delay per gate at 2 V power supply and 25°C ambient. The average power dissipation is about 0.8 mW per gate. Best wafer yield of 14% was observed. This indicate that high-speed circuits with 3.5 K gate complexity can be implemented in the present SARGIC HFET technology in a pilot line environment. The ALU chip has input data register and output data register which can be clocked by independent signals. The propagation delay through a critical path between the registers is measured by moving the output clock edge towards the input clock edge until the chip fails