A new architecture of EEPROM for high density and high reliability application

A concept of dual-control gate EEPROM cell and array architecture are proposed. New programming conditions used for write and erase operations are developed to improve the lifetime of the cell. This approach allows a programming of the cell only by the top of the structure without bias on the drain-bulk or source-bulk junctions. Moreover, compared to the standard FLOTOX EEPROM, the select transistor has been eliminated, thus attaining a single transistor configuration so a high density memory cell. A compact model and 2D numerical simulation show that the basic functions of this cell, namely reading, programming and erasing are possible with a suitable setting of the applied voltages. Scalability and endurance potentiality make this cell interesting for future high-density and high reliability applications.