Adaptable ferroelectric memories for space applications

Test results on a 1 kilobit prototype hardened-by-design ferroelectric memory show that the total dose hardness exceeds 2 Mrads and latch-up immunity exceeds 163 LET. Based on the proven prototype memory design concepts, a 2 Mbit hardened-by-design ferroelectric memory for space applications is being designed for fabrication on the 0.13 μm ferroelectric process of Texas Instruments. A subsequent chip design is expected to be at a 32 Mbit density. Using die stack packaging techniques, components at densities up to 256 Mbits based on this design may be developed. The basic ferroelectric memory core can be combined with on-chip interface circuitry to emulate any number of traditional semiconductor memory architectures, including SRAM, SDRAM, EEPROM and Flash memory, for applications ranging from small boot memories to high-density mass memories. The very fast read and write times of ferroelectric memory, coupled with the ability to trade off internal write voltage with retention and endurance, enable an adaptable ferroelectric memory technology. Texas Instrument´s design rules for ferroelectric memory processes at 0.13 μm and 0.09 μm are competitive with the most aggressive design rules used for other semiconductor memory types.