Design-kit development based upon ISsiT´s CMOS 1µM process technology

Author

Chenouf, A. ; Slimane, A. ; Berrandjia, M.L. ; Oudjida, A.K. ; Smatti, A. ; Akak, L.

Author_Institution

Adv. Technol. Dev. Centre, CDTA, Microelectron. & Nanotechnol. Lab., Algiers, Algeria

fYear

2010

fDate

27-30 June 2010

Firstpage

1

Lastpage

4

Abstract

This paper summarizes the necessary steps we went through to develop a design-kit for full-custom design based upon ISiT´s CMOS 1 μm technology process. All basic information dealing with technology setup, rule decks and analog simulation environment is provided and commented. The design-kit is fully compliant with Cadence Generic Process Design-Kit (GPDK) methodology guide, revision 1.8, September 2002. It has been developed using Cadence IC-Package IC5.1.41 tool-chain version, running under Solaris 10 OS. To validate our design-kit, an inverter cell has been designed according to the standard full-custom design flow.

Keywords

CMOS integrated circuits; technology CAD (electronics); CMOS process technology; analog simulation environment; design-kit; rule decks; technology setup; Capacitance; Design automation; Inverters; Layout; Libraries; Solid modeling; Time division multiplexing; CMOS Process Technology; Cadence CAD Tools; Clean-room; Design-Kit (DK);

fLanguage

English

Publisher

ieee

Conference_Titel

Systems Signals and Devices (SSD), 2010 7th International Multi-Conference on

Conference_Location

Amman

Print_ISBN

978-1-4244-7532-2

Type

conf

DOI

10.1109/SSD.2010.5585597

Filename

5585597