A low power 12-bit 40MS/s pipelined ADC with digital calibration

This paper presents a 12-bit 40 MS/s pipelined ADC fabricated in a 0.18 mum CMOS process. A simple open-loop residue amplifier is used in first stage to reduce power dissipation and increase circuit speed. The errors caused from open-loop amplifier are evaluated and calibrated by a statistics-based background calibration technology. A new circuit topology of open-loop amplifier is presented in this paper in order to achieve low-voltage and low-power requirements. Also, a proposed (1+1)-bit/stage structure for pipelined ADC is used to convert residue voltage that may exceed the convert range of the ADC. The active area of the ADC is 3.2times3.7 mm² and the power consumption equals 210 mW from a 1.8-V supply.