Title :
A video rate rerastering IC
Author :
Mayweather, William, III
Author_Institution :
David Sarnoff Res. Center, Princeton, NJ, USA
Abstract :
A video mapping IC developed for the real-time compression and expansion of raster-scanned video lines in the generation of NTSC-compatible HDTV signals is described. The circuit is implemented with standard cells and contains 70000, 1.5 μm, CMOS transistors. The device performs a four-point nonlinear interpolation, contains a 200 pixel dual-port RAM, is serially configurable, and operates at 14.3 MHz. Simulation was used to determine subjective acceptable interpolation resolution. A FORTRAN program was written to implement the peaked interpolation algorithm
Keywords :
CMOS integrated circuits; VLSI; colour television; data compression; digital integrated circuits; high definition television; interpolation; picture processing; video signals; 1.5 micron; 14.3 MHz; CMOS transistors; FORTRAN program; NTSC-compatible HDTV signals; dual-port RAM; four-point nonlinear interpolation; peaked interpolation algorithm; raster-scanned video lines; real-time compression; serially configurable; standard cells; video mapping IC; video rate rerastering IC; Application specific integrated circuits; Circuit testing; Clocks; Decoding; Frequency; HDTV; Image coding; Interpolation; TV; Video compression;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124795
