Title :
A two-stage pipelined passive charge-sharing SAR ADC
Author :
Imani, Alireza ; Bakhtiar, Mehrdad Sharif
Author_Institution :
Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran
fDate :
Nov. 30 2008-Dec. 3 2008
Abstract :
This paper presents a new ADC based on using passive charge sharing SAR ADC in a 2-stage pipeline architecture. The charge domain operation of passive charge sharing ADC poses an inherent limitation on its resolution. The proposed architecture increases the achievable resolution with a low power overhead. Designed and simulated in a 0.18 um CMOS process, the 12-bits, 40 MS/sec ADC core consumes 7 mW from a 1.8 V supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; passive networks; synthetic aperture radar; 2-stage pipeline architecture; ADC; CMOS; SAR; passive charge sharing; power 7 mW; size 0.18 mum; voltage 1.8 V; word length 12 bit; CMOS process; Capacitors; Circuits; Performance analysis; Pipeline processing; Power supplies; Sampling methods; Signal sampling; Switches; Voltage;
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
DOI :
10.1109/APCCAS.2008.4745980
