A new wideband, high-linear passive Sample and Hold structure suitable for high-speed, high-resolution ADCs

Author

Sadeghipour, Khosrov Dabbagh

Author_Institution

Marand Eng. Fac., Univ. of Tabriz, Tabriz

fYear

2008

fDate

Nov. 30 2008-Dec. 3 2008

Firstpage

149

Lastpage

152

Abstract

In this paper a new passive sample and hold (S/H) structure employing a modified sampling switch circuit has been presented. In order to reach wideband input with high linear sampling, the sampling switch voltage dependency on input signal is reduced, dramatically. Furthermore, the proposed structure reduces signal feedthrough for high frequency inputs as well as enabling the merge of offset cancellation cycle for S/H subsequent stage with the sampling cycle, simultaneously. The simulation results for the designed 12-bit, 250 Msps S/H in standard 0.35 mum CMOS process with 500 MHz input bandwidth, show 14 dB and 10 dB improvement on THD and signal feedthrough, respectively.

Keywords

CMOS integrated circuits; analogue-digital conversion; sample and hold circuits; CMOS process; analogue-digital conversion; high-linear sample and hold structure; high-resolution ADC; high-speed ADC; passive sample and hold structure; sampling switch circuit; size 0.35 mum; word length 12 bit; Bandwidth; CMOS process; Frequency; Sampling methods; Signal design; Signal sampling; Switches; Switching circuits; Voltage; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on

Conference_Location

Macao

Print_ISBN

978-1-4244-2341-5

Electronic_ISBN

978-1-4244-2342-2

Type

conf

DOI

10.1109/APCCAS.2008.4745982

Filename

4745982