Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set (2n,2n+1−1,2n−1)

The moduli set M₁=(2ⁿ,2ⁿ⁺¹-1,2ⁿ-1) which is free of 2^a+1 modulus is profitable to construct a high-speed residue number system (RNS). In this paper, we derive a reduced-complexity residue-to-binary conversion algorithm for M₁ by using new Chinese remainder theorem (CRT). The resulting converter architecture mainly consists of carry-save adders (CSAs), modular adders and multiplexer (MUX) which is suitable for an efficient VLSI implementation. Under the same dynamic range (DR) requirement, the proposed converter design is significantly more efficient than the latest design for M₁ with respect to area-time (AT), time-power (TP) and area-time-power (ATP) products. Based on UMC 0.18 um CMOS cell-based technology, the chip area for 16-bit residue-to-binary converter is only 931times931um² and the working frequency is 135 MHz.