Title :
A general purpose high speed equalizer
Author :
Maginot, S. ; Balestro, F. ; Joanblanq, C. ; Senn, P. ; Palicot, J.
Author_Institution :
CNET, Meylan, France
Abstract :
The circuit presented is a high-speed self-adaptive filter achieving equalization over a wide range of signals, with a frequency of up to 40.5 MHz, such as the European D2-MAC and HD-MAC transmission standards. This 105000-transistor chip has been designed in a CMOS 1.0-μm technology and is being used in a D2-MAC reception environment. In addition to the cabled D2MAC environment, this circuit can be implemented in such applications such as HDTV (HDMAC via satellite transmission). Its frequency (up to 40.5 MHz) and its flexibility due to programmable parameters allow this chip to be integrated in a wide range of systems
Keywords :
CMOS integrated circuits; adaptive filters; cable television; direct broadcasting by satellite; equalisers; high definition television; 1.0 micron; CMOS; D2-MAC; HD-MAC; HDMAC; HDTV; cabled D2MAC environment; high speed equalizer; programmable parameters; satellite transmission; self-adaptive filter; transmission standards; Bandwidth; CMOS technology; Circuits; Equalizers; Frequency; HDTV; Sampling methods; Standards development; TV; Transversal filters;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124799
