An ultra low-power Successive Approximation ADC using an offset-biased auto-zero comparator

This paper presents a new offset-biased autozero comparator for the design of an ultra low-power charge redistribution successive approximation analog-to-digital converter (SA-ADC) dedicated to biomedical applications. The circuits are realized in CSM 0.18 mum CMOS technology. The simulated results have shown that the power consumption of the 10-bit ADC is only 6.2 muW at a single supply of 1.8 V whilst sampling at a frequency of 64 kHz, with conversion time of 187.5 vs. The energy per quantization level is less than 0.1pJ/level.