An ultra low-power Successive Approximation ADC using an offset-biased auto-zero comparator

Author

Susanti, Y. ; Chan, P.K. ; Ong, V. K S

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore

fYear

2008

fDate

Nov. 30 2008-Dec. 3 2008

Firstpage

284

Lastpage

287

Abstract

This paper presents a new offset-biased autozero comparator for the design of an ultra low-power charge redistribution successive approximation analog-to-digital converter (SA-ADC) dedicated to biomedical applications. The circuits are realized in CSM 0.18 mum CMOS technology. The simulated results have shown that the power consumption of the 10-bit ADC is only 6.2 muW at a single supply of 1.8 V whilst sampling at a frequency of 64 kHz, with conversion time of 187.5 vs. The energy per quantization level is less than 0.1pJ/level.

Keywords

CMOS integrated circuits; analogue-digital conversion; biomedical electronics; comparators (circuits); low-power electronics; CSM CMOS technology; analog-to-digital converter; auto-zero comparator; biomedical applications; power 6.2 muW; size 0.18 mum; successive approximation; ultra low-power electronics; voltage 1.8 V; word length 10 bit; CMOS technology; Capacitors; Circuit topology; Energy consumption; Latches; Logic devices; Preamplifiers; Sampling methods; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on

Conference_Location

Macao

Print_ISBN

978-1-4244-2341-5

Electronic_ISBN

978-1-4244-2342-2

Type

conf

DOI

10.1109/APCCAS.2008.4746015

Filename

4746015