Improving the design of parallel-pipeline cyclic decoders towards fault-secure versions

In this paper, we consider the problem of designing fault-secure decoders for various cyclic linear codes. The principle relies on a slight modification of the high speed parallel-pipeline decoder architecture in [6], to control the correct operation of the cyclic decoder as well. The complexity evaluation has been obtained by synthesizing parallel-pipeline decoder for various code on a Stratix II FPGA using the Alterapsilas Quartus II software. It shows that their FS versions compare favorably against the unprotected ones, with respect to the area and the maximal operation frequency.