Adjustable low consumption circuit for monitorization of power source voltages in a SoC

This paper proposes an architecture for a power good comparator (PGC) designed to be used in the monitorization of supply voltages of a system-on-chip (SoC). The architecture includes a string of resistors, a comparator, a programmable debouncer and two multiplexers. This architecture was design for very low power consumption and to monitor 4 VDDs. I was implemented using TSMC 65 nm CMOS technology for VDD values of 0.9, 1.2, 1.8 and 3.3 V, with 8 programmable levels of debouncing from 3.2 mus to 32.4 mus. The PGC maximum consumption is 3.54 muA. The output signal presents a digitally adjustable hysteresis curve, with a high threshold voltage of 93% and a low threshold voltage of 90% of VDD. Practical implementation details are presented, namely the requirement for level-converters and for a bulk bias selector in the input multiplexer.