• DocumentCode
    2324301
  • Title

    A New Application-Tuned Processor Architecture for High-Performance Reconfigurable Computing

  • Author

    Shang, Li-Hong ; Zhou, Mi ; Zhang, Jiong ; Li, Hong-Bin

  • Author_Institution
    Sch. of Comput. Sci. & Eng., Beihang Univ., Beijing, China
  • fYear
    2009
  • fDate
    July 29 2009-Aug. 1 2009
  • Firstpage
    138
  • Lastpage
    143
  • Abstract
    One design goal of future processors is to maximize the performance per watt. However, the performance of general purpose processors can be hardly improved by barely increasing clock frequency. This paper presents an application specific reconfigurable processor architecture which is fine tuned for high performance computing. It benefits from the application specific hardware customized to significantly improve its efficiency. In comparison with the existing work on configurable processor architectures, the proposed architecture has higher functional density and lower power consumption per inch due to its runtime partial reconfiguration ability. Moreover, it can adaptively change its architecture to further promote the average performance and feasibility for other applications.
  • Keywords
    logic design; microprocessor chips; power aware computing; reconfigurable architectures; application specific reconfigurable processor architecture; application-tuned processor architecture; high-performance reconfigurable computing; power consumption; Adaptive systems; Application specific processors; Computer applications; Computer architecture; Coprocessors; Hardware; High performance computing; Instruction sets; NASA; Runtime; application-tuned processor architecture; reconfigurable computing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Adaptive Hardware and Systems, 2009. AHS 2009. NASA/ESA Conference on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    978-0-7695-3714-6
  • Type

    conf

  • DOI
    10.1109/AHS.2009.18
  • Filename
    5325459