A dynamic CMOS multiplier for analog neural network cells

Author

Massengill, L.

Author_Institution

Dept. of Electr. Eng., Vanderbilt Univ., Nashville, TN, USA

fYear

1990

fDate

13-16 May 1990

Abstract

A strobed multiplier circuit for use in integrated neural network architectures is presented. The circuit, which can be fabricated in a standard CMOS analog process, performs the two-quadrant weighting of interconnect signals via exponential charge packets onto capacitive summing buses. SPICE simulations and MOSIS fabrication results are presented. The proposed design is simple in structure, uses no operational amplifiers for the actual multiplication function, uses no power in the static mode, and has been implemented in standard 2 μm analog CMOS processing

Keywords

CMOS integrated circuits; analogue circuits; circuit analysis computing; multiplying circuits; neural nets; 2 micron; MOSIS fabrication results; SPICE simulations; analog neural network cells; capacitive summing buses; dynamic CMOS multiplier; exponential charge packets; interconnect signals; strobed multiplier circuit; two-quadrant weighting; CMOS analog integrated circuits; CMOS process; Circuit simulation; Fabrication; Integrated circuit interconnections; Neural networks; Operational amplifiers; Power amplifiers; SPICE; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124805

Filename

124805