A time-domain layered finite element reduction recovery method (LAFE-RR) for high-frequency VLSI design

In this paper, we develop a time-domain layered finite element reduction recovery (TD-LAFE-RR) method to solve large-scale IC design problems at high frequencies. This method rigorously reduces the matrix of the original multilayer system to that of a single-layer no matter how large the original problem is. More importantly, the matrix reduction is achieved analytically, and hence the CPU and memory overheads are minimal. Compared to the layered finite-element method we developed earlier, the proposed method further improves the modeling capacity and performance since the matrix reduction is achieved analytically. In addition, developed in time domain, the method permits nonlinear modeling and broadband simulation within one run. Numerical results are given to demonstrate the accuracy and efficiency of the proposed method.