Title :
A high-speed key exchange multi-core SoC architecture for IPSec real-time Internet traffic
Author :
Moore, Patrick ; O´Neill, Maire ; McLaughlin, Kieran ; Sezer, Sakir
Author_Institution :
ECIT Inst., Queen´´s Univ. Belfast, Belfast, UK
Abstract :
This paper presents a scalable and flexible multi-core SoC architecture for high-speed key exchange for emerging IP security systems. Novel approaches are proposed for HMAC authentication block parallelization, distributed key handling and a pipelined block cipher design that allows feedback encryption modes. This improves upon previous state-of-the-art designs for IPSec, creating an architecture suitable for delivering emerging secure high-speed streaming applications via the Internet.
Keywords :
Internet; cryptography; microprocessor chips; multiprocessing systems; system-on-chip; telecommunication security; HMAC authentication block parallelization; IP security system; IPSec real-time Internet traffic; distributed key handling; feedback encryption mode; flexible multicore SoC architecture; high speed key exchange multicore SoC architecture; high speed streaming application; pipelined block cipher design; scalable multicore SoC architecture; Cryptography; Field Programmable Gate Arrays; Internet; Security;
Conference_Titel :
GLOBECOM Workshops (GC Wkshps), 2010 IEEE
Conference_Location :
Miami, FL
Print_ISBN :
978-1-4244-8863-6
DOI :
10.1109/GLOCOMW.2010.5700456