• DocumentCode
    2325357
  • Title

    A sub-1 volt CMOS bandgap reference with high power supply rejection

  • Author

    Somvanshi, Sameer

  • Author_Institution
    EEE Dept., Birla Inst. of Technol. & Sci., Pilani
  • fYear
    2008
  • fDate
    Nov. 30 2008-Dec. 3 2008
  • Firstpage
    666
  • Lastpage
    667
  • Abstract
    This paper presents the modification of the authorpsilas previous paper. This paper necessarily extracts the benefit of getting the sub-1 voltage from the circuit of all CMOS, with low temperature coefficient of 34.3 ppm/muC. This circuit has an added advantage of high power supply rejection of -37 dB from DC to high frequency. Also, with work has been implemented on higher technology node of 130 nm compared to that 180 nm of paper, essentially resulting into lower area of 0.0035 mm2.
  • Keywords
    CMOS integrated circuits; energy gap; CMOS bandgap reference; high power supply rejection; temperature coefficient; voltage 1 V; CMOS technology; Equations; Fluctuations; Frequency; MOSFET circuits; Paper technology; Photonic band gap; Power supplies; Temperature; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
  • Conference_Location
    Macao
  • Print_ISBN
    978-1-4244-2341-5
  • Electronic_ISBN
    978-1-4244-2342-2
  • Type

    conf

  • DOI
    10.1109/APCCAS.2008.4746111
  • Filename
    4746111
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2325357