A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisition

This paper describes a 1.25-Gb/s all-digital clock and data recovery (ADCDR) circuit with binary frequency acquisition which is never achieved in reference-less ADCDR systems. The proposed configuration of digital loop filter without any adder can minimize to loop latency and the recovered clock jitter. The proposed ADCDR circuit occupies a chip area of 0.9times0.7 mm² and consumes 80 mW from a single 1.8-V power supply. Simulation results show the binary frequency acquisition time is less than 500 ns and the total lock time is less than 800 ns while receiving a 1.25 Gb/s NRZ data. The recovered eye diagram exhibits 45 ps peak-peak jitter.