Title :
Direct solution of performance constraints during placement
Author :
Chao, Albert ; Nequist, Eric ; Vuong, Thanh
Author_Institution :
Cadence Design Syst. Inc., San Jose, CA, USA
Abstract :
A practical set of features for meeting the constraints of high performance designs during placement has been developed. The tool observes signal path constraints in units of time, automatically trading off delay between nets on the critical paths. The tool can observe net constraints in units of delay or capacitance. These features are based on a fast and accurate algorithm for net wiring estimation. Using a constraints method enables the true timing problem to be solved better and eliminates design iteration. Additional features specific to ECL design are also available. Results show a 52% reduction in interconnect delay versus an unconstrained placement on the first test case
Keywords :
circuit layout; delays; emitter-coupled logic; logic design; wiring; ECL design; critical paths; delay; high performance designs; interconnect delay; net wiring estimation; performance constraints; placement; signal path constraints; Automatic control; Capacitance; Clocks; Delay; Integrated circuit interconnections; Latches; Logic design; Timing; Wire; Wiring;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124811
