Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

Recently a demand for high-speed wireless network service on mobile devices is rapidly increasing. Error correcting codes are used to enhance network communication quality. Particularly, LDPC (low density parity check) codes show high throughput and achieve information rates very close to the Shannon limit. In this paper, we propose a dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding. Our proposed decoder deals with multi-rate codes by introducing a multi-rate compatible 1st-2nd minimum searching unit. The proposed decoder shows the better throughput over the wide range of S/N ratio compared to conventional rate-fixed LDPC decoders.