An FPGA implementation of a DWT with 5/3 filter using semi-programmable hardware

The discrete wavelet transform with 5/3 filter of the JPEG2000 shows different memory access patterns according to the levels of decomposition. To make computation faster by hardware implementation, hiding memory access latency is important to improve a performance. The semi-programmable hardware (SPWH) as an intermediate hardware provides an efficient design method of a hardware with data prefetching to hide the memory access latency across the different memory access patterns. This paper describes the SPHW and demonstrates a mapping method for the DWT. The experimental result shows that the SPHW can significantly reduce a design burden and achieve a good performance.