Arithmetic reduction of adder leakage in nanoscale CMOS

In todaypsilas technology generations, e.g. 90 and 65 nm, the static power consumption becomes a major contributor to the total power consumption. It is therefore important to consider all abstraction levels to reduce this power. This paper focuses on the arithmetic level and shows a methodology for a substantial reduction of the static power consumption. Both the dynamic and static power consumption is evaluated for bit-parallel and bit-serial arithmetic. Simulations are done in a typical 130 nm technology. With only a minor cost in dynamic power consumption, a static power reduction up to 13 times is shown by using bit-serial arithmetic.