Title :
A novel configurable no dead-zone digital phase detector design
Author :
Wang, Min ; Zhiping Wen ; Che, Lei ; Zhang, Yanlong
Author_Institution :
BMTI, Beijing Microelectron. Tech. Instn., Beijing
fDate :
Nov. 30 2008-Dec. 3 2008
Abstract :
A novel configurable no dead-zone digital phase detector is proposed in this paper. As an embedded SRAM is employed to store configuration data, detection sensitivity of the phase detector can be controlled by the configuration data according to different input frequency. Besides, the novel phase detector avoid dead-zone by adopting two flip-flops and generating three state during operation. The circuit can be part of a standard digital cell library and can easily be used in field programmable gate array (FPGA). The PD is designed to betake in the frequency range of 25 MHz to 200 MHz. Simulation result for the proposed circuit realized with 0.18 um CMOS technology.
Keywords :
SRAM chips; flip-flops; phase detectors; dead zone detection; digital phase detector; embedded SRAM; field programmable gate array; flip-flops; frequency 25 MHz to 200 MHz; size 0.18 micron; CMOS technology; Circuits; Clocks; Delay; Field programmable gate arrays; Flip-flops; Phase detection; Phase frequency detector; Phase locked loops; Random access memory;
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
DOI :
10.1109/APCCAS.2008.4746125
