A novel configurable no dead-zone digital phase detector design

A novel configurable no dead-zone digital phase detector is proposed in this paper. As an embedded SRAM is employed to store configuration data, detection sensitivity of the phase detector can be controlled by the configuration data according to different input frequency. Besides, the novel phase detector avoid dead-zone by adopting two flip-flops and generating three state during operation. The circuit can be part of a standard digital cell library and can easily be used in field programmable gate array (FPGA). The PD is designed to betake in the frequency range of 25 MHz to 200 MHz. Simulation result for the proposed circuit realized with 0.18 um CMOS technology.