Title :
A power-gating scheme for CAL circuits using single-phase power-clock
Author :
Zhang, Weiqiang ; Su, Li ; Fu, Jinghong ; Hu, Jianping
Author_Institution :
Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo
fDate :
Nov. 30 2008-Dec. 3 2008
Abstract :
This paper presents a power-gating scheme for CAL (clocked adiabatic logic) circuits to reduce energy loss during idle state. A transmission gate is used as the power-gating switch. It is inserted between the single-phase power-clock and virtual power-clocks to detach power-gated CAL logic blocks during idle periods. The 8-bit full adders based on the CAL circuits are used to verify the proposed power-gating technique. All circuits are simulated using the BSIM3V3 models of TSMC 0.18 mum CMOS technology. Energy loss can be reduced greatly by shutting down idle adiabatic logic blocks.
Keywords :
CMOS integrated circuits; clocks; logic circuits; 8-bit full adders; CAL circuits; CMOS technology; clocked adiabatic logic circuits; detach power-gated CAL logic blocks; power-gating scheme; power-gating switch; single-phase power-clock; transmission gate; virtual power-clocks; Adders; CMOS logic circuits; CMOS technology; Circuit simulation; Clocks; Energy loss; Logic circuits; MOSFETs; Switches; Voltage;
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
DOI :
10.1109/APCCAS.2008.4746155