Estimating the quality of complexity measures in heuristics for reversible logic synthesis

Reversible circuits have been intensively studied in recent years due to their applications in many areas, including quantum computing, nanotechnology and low-power design. Synthesis of reversible circuits differs significantly from the traditional logic synthesis. No satisfactory synthesis algorithm has been proposed for such circuits so far. All existing heuristic approaches to reversible logic synthesis utilize complexity measures. In this paper such complexity measures are analyzed and quantitative comparison of these approaches is presented. Possibilities for improving heuristic algorithms for reversible circuit synthesis are also discussed.