DocumentCode
2326618
Title
CTH14-6: Error Correction Using a Message-Passing Decoder to Process Cyclic Redundancy Checks
Author
Spencer, Quentin H.
Author_Institution
Distrib. Control Syst., Inc., Hazelwood, MO
fYear
2006
fDate
Nov. 27 2006-Dec. 1 2006
Firstpage
1
Lastpage
5
Abstract
This paper proposes a method for correcting errors in messages encoded using cyclic redundancy checks (CRCs), which are typically only used for error detection. This is accomplished for messages of a known length by deriving a parity-check matrix representation of the CRC. The parity-check matrix can then be used to correct errors using the message-passing decoder (MPD) commonly used to decode LDPC codes. The CRC parity-check matrix is not sparse, which inhibits performance of the MPD, but this effect can be reduced by modifying the matrix using recently proposed sparsification techniques to eliminate short cycles. The technique is practical mainly for codes with short block sizes, and can also be applied to coding schemes that concatenate a CRC with an outer error correcting code. Simulation results demonstrate some performance gains, although less than what can be gained using custom-designed LDPC codes for the same rate and message length.
Keywords
concatenated codes; cyclic redundancy check codes; error correction codes; error detection; message passing; parity check codes; LDPC codes; concatenated code; cyclic redundancy checks; error correction; error detection; message-passing decoder; parity-check matrix representation; short block sizes; sparsification techniques; Block codes; Cyclic redundancy check; Error analysis; Error correction; Error correction codes; Hardware; Iterative decoding; Linear feedback shift registers; Parity check codes; Sparse matrices;
fLanguage
English
Publisher
ieee
Conference_Titel
Global Telecommunications Conference, 2006. GLOBECOM '06. IEEE
Conference_Location
San Francisco, CA
ISSN
1930-529X
Print_ISBN
1-4244-0356-1
Electronic_ISBN
1930-529X
Type
conf
DOI
10.1109/GLOCOM.2006.116
Filename
4150746
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