DocumentCode
2326664
Title
Testing embedded RAMs in ASIC chips
Author
Fasang, Patrick
Author_Institution
Nat. Semicond. Corp., Santa Clara, CA, USA
fYear
1990
fDate
13-16 May 1990
Abstract
The problems, issues, and solutions for testing RAMs which are embedded in ASIC chips are presented. Testing RAMs requires a test strategy different from that used to test random logic because RAMs have more fault types. In general, for a given fault model such as the stuck-at one/zero model, testing a RAM requires more test vectors than testing a random-logic circuit of the same number of equivalent gates. Embedded RAMs are even more difficult to test because of the limited access to the original nodes of the RAMs
Keywords
application specific integrated circuits; fault location; integrated circuit testing; logic testing; random-access storage; ASIC chips; embedded RAMs; equivalent gates; fault types; limited access; stuck-at one/zero model; test strategy; test vectors; Application specific integrated circuits; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Logic circuits; Logic testing; Pins; Random access memory; Read-write memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location
Boston, MA
Type
conf
DOI
10.1109/CICC.1990.124819
Filename
124819
Link To Document