Single-phase power-gating adiabatic flip-flops

This paper presents low-power power-gating adiabatic flip-flops using single-phase power-clock scheme. The proposed power-gating adiabatic flip-flops are realized with improved CAL (Clocked Adiabatic Logic) circuits. The refresh enable terminals are added for power-gating operation. A power-gating scheme for the single-phase adiabatic sequential circuits is described. The two power-gating switches are inserted between the single-phase power-clock and virtual power-clocks to detach power-gated sequential logic blocks and to refresh the storage value of power-gating adiabatic flip-flops during idle periods. A practical sequential system realized with the proposed single-phase power-gating adiabatic flip-flops is demonstrated. SPICE simulations show that energy loss of the single-phase adiabatic sequential circuits can be greatly reduced by shutting down adiabatic logic blocks during idle periods.