An FPGA architecture for real-time polyphase 2D FIR double-trapezoidal plane-wave filters

An architecture is proposed for the real-time hardware implementation of beamforming polyphase 2D FIR double-trapezoidal filters. Such filters are useful for high-throughput real-time beamforming of temporally-broadband band-pass spatio-temporal (ST) plane-waves (PWs). The single-chip implementation of a cluster of identical prototype building block circuits is described for a Xilinx Virtex-4 Stimes35 ff668-10 FPGA chip and tested using on-chip stepped hardware co-simulation. Also, a method is described for minimizing the signal distortion at the output of the beamformer due to finite wordlength effects.