Title :
Timing variation-aware high level synthesis: Current results and research challenges
Author :
Jung, Jongyoon ; Kim, Taewhan
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul
fDate :
Nov. 30 2008-Dec. 3 2008
Abstract :
The timing closure problem is one of the most important problems to be addressed at all levels of the synthesis process. Currently, the timing problem is much complicated due to the presence of process variation. Recently in high-level synthesis (HLS), a shift in the timing analysis, from deterministic timing to statistical timing, to reflect the impact of the timing variation on the quality of results becomes an important research topic where the major considerations are the accurate statistical timing analysis of datapath and the tight and full integration of the SSTA into HLS framework. In this paper, we survey and discuss the state-of-art timing variation-aware HLS techniques, with the classification of (1) SSTAs for HLS, (2) HLS framework using SSTAs, and (3) limitations of the work, with suggestions on the future research directions.
Keywords :
network synthesis; statistical analysis; timing circuits; deterministic timing; statistical timing; timing closure; timing variation-aware high level synthesis; Adders; Computer science; Delay; Flow graphs; High level synthesis; Job shop scheduling; Logic circuits; Logic design; Timing; Yield estimation;
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
DOI :
10.1109/APCCAS.2008.4746194