Title :
A universal test sequence for CMOS scan registers
Author :
Lee, Kuen-Jong ; Breuer, Melvin
Author_Institution :
Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
A systematic method for analyzing all possible faults within the scan path of a scan-based CMOS circuit is given. The analysis shows that both logic and current monitoring are necessary in order to detect all irredundant faults. A universal test sequence is derived based on the analysis of single bridging faults. This sequence also detects all irredundant stuck-at and stuck-open faults. SPICE simulations show that CSM (current supply monitoring) method is an effective method for detecting some bridging faults
Keywords :
CMOS integrated circuits; digital simulation; fault location; logic testing; shift registers; CMOS scan registers; SPICE simulations; current monitoring; current supply monitoring; faults; irredundant faults; scan path; single bridging faults; stuck-at faults; stuck-open faults; universal test sequence; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Current supplies; Electrical fault detection; Fault detection; Monitoring; Registers; SPICE;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124822
