An FPGA implementation of 1,024-neuron system for PAPR reduction of OFDM signal

Author

Ohta, Masaya ; Mori, Atsushi ; Yamashita, Katsumi

Author_Institution

Dept. of Electr. & Electron. Syst., Osaka Prefecture Univ., Sakai, Japan

Volume

4

fYear

2004

fDate

25-29 July 2004

Firstpage

2625

Abstract

The aim of this paper is to reduce computational complexity of the neural network for PAPR reduction of OFDM signal, and to implement the neural network including 1,024 neurons by FPGA for practical OFDM transmitter of the terrestrial digital broadcast. A couple of IDFTs reduce computational complexity of the neuron updating from O(N²) to O(N log N). This neural network is designed using VHDL for Xilinx FPGA device, XC2V6000, and 1,024-neuron system is implemented by less than 30% of resources of the device.

Keywords

OFDM modulation; computational complexity; field programmable gate arrays; hardware description languages; neural nets; 1,024-neuron system; FPGA implementation; IDFT; OFDM signal; PAPR reduction; VHDL; Xilinx FPGA device; computational complexity; field programmable gate array; neural network; orthogonal frequency-division multiplexing; peak-to-average power ratio; terrestrial digital broadcast; Computational complexity; Field programmable gate arrays; Hopfield neural networks; Neural network hardware; Neural networks; Neurons; Neurotransmitters; OFDM modulation; Peak to average power ratio; Quadrature phase shift keying;

fLanguage

English

Publisher

ieee

Conference_Titel

Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on

ISSN

1098-7576

Print_ISBN

0-7803-8359-1

Type

conf

DOI

10.1109/IJCNN.2004.1381060

Filename

1381060