DocumentCode
2327512
Title
CPCA: a multiplierless neural PCA
Author
Dogaru, Radu ; Dogaru, Ioana ; Glesner, Manfred
Author_Institution
Dept. of Appl. Electron. & Information Eng., Bucharest Polytech Univ., Romania
Volume
4
fYear
2004
fDate
25-29 July 2004
Firstpage
2689
Abstract
A multiplier-less neural architecture for PCA is proposed. The aim is to reduce the VLSI complexity of its implementation by eliminating the multipliers. Comparisons with standard PCA methods show no degradation in performances (in most cases they are even improved) while the reduced hardware complexity allows for efficient low power implementations.
Keywords
VLSI; principal component analysis; CPCA; VLSI complexity; multiplierless neural PCA; Degradation; Discrete cosine transforms; Electronic mail; Hardware; Information processing; Microelectronics; Neurons; Principal component analysis; Ubiquitous computing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on
ISSN
1098-7576
Print_ISBN
0-7803-8359-1
Type
conf
DOI
10.1109/IJCNN.2004.1381075
Filename
1381075
Link To Document