Fast locking and high accurate current matching phase-locked loop

Author

Liu, Silin ; Shi, Yin

Author_Institution

Inst. of Semicond., Chinese Acad. of Sci., Beijing

fYear

2008

fDate

Nov. 30 2008-Dec. 3 2008

Firstpage

1136

Lastpage

1139

Abstract

In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PLL circuit is designed based on the 0.35 um 2P4M CMOS process with 3.3 V/5 V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PLL and its charge pump sink and source current mismatch is only 0.008%.

Keywords

CMOS integrated circuits; charge pump circuits; integrated circuit design; phase locked loops; 2P4M CMOS process; HSPICE simulation; current matching characteristics; differential charge pump based phase-locked loop; fast locking CPLL; size 0.35 mum; source current mismatch; voltage 3.3 V; voltage 5 V; Bandwidth; CMOS process; Charge pumps; Circuits; Clocks; Delay; Phase frequency detector; Phase locked loops; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on

Conference_Location

Macao

Print_ISBN

978-1-4244-2341-5

Electronic_ISBN

978-1-4244-2342-2

Type

conf

DOI

10.1109/APCCAS.2008.4746225

Filename

4746225